A lot of retention across a power cycle relies on internal capacitance. The charge held on such a capacitor decays over time.
A mapper stores its state in latches, also called static random access memory (SRAM) cells. These consist of four transistors to implement a pair of 2-transistor NAND gates, each acting as an inverter to hold the other gate's input voltage at the opposite of its own input voltage. There are maybe 2 more gates per cell to update the voltages when writing a bit. If the transistors on one side of the SRAM cell are stronger than the other, that cell will power on with a 0; otherwise, it will power on with a 1. And sometimes the transistors are close enough in strength that variations in temperature, process, and voltage can change the power-up state from one unit to another or even from one run to another on the same unit.
A mapper stores its state in latches, also called static random access memory (SRAM) cells. These consist of four transistors to implement a pair of 2-transistor NAND gates, each acting as an inverter to hold the other gate's input voltage at the opposite of its own input voltage. There are maybe 2 more gates per cell to update the voltages when writing a bit. If the transistors on one side of the SRAM cell are stronger than the other, that cell will power on with a 0; otherwise, it will power on with a 1. And sometimes the transistors are close enough in strength that variations in temperature, process, and voltage can change the power-up state from one unit to another or even from one run to another on the same unit.
Statistics: Posted by tepples — Tue Dec 10, 2024 9:03 pm
