NES Hardware and Flash Equipment • Re: Guessing things from cartridge connector signals

2) Detect power/reset state via CPU A0
During normal CPU operation, A0 can be held in same state not longer than for 5 cycles
It also becomes high impedance when RESET is held. So similar reset detector like for M2.

The longest A0 can be held in one state is for example:
ASL $0001,X ;assuming that X==$FF

Code:

A0      |      0       |     1  |    0  |    0  |    0  |    0      |    0  |   1   |A       | $8000        | $8001  | $8002 | $0000 | $0100 | $0100     | $0100 | $8003 |D       | $1E          | $01    | $00   | $00   | $00   | $00       | $00   |       |R/W     | R            | R      | R     | R     | R     | R         | W     |       |comment | ASL $0001, X | read   | read  | read  | read  | do math   | write |       |        |    (X==$FF)  | LO     | HI    | mem   | val   | operation |       |       |        |              | arg    | arg   | val   | again |           |       |       |

Or maybe there exist longer one?

With DMA, it should be able to stay even for much more than 5 cycles. A 9 cycle sequence with DMC DMA during OAM DMA should be possible using something like STA ($01),Y where the pointer points at $4014 and Y is 0:

Read $01 for low pointer byte
----Even A0's start here-----
Read $02 for high pointer byte
Read $4014 for index adjustment
Write $4014 (put)
Read even PC address (get) [DMA halt]
Read even PC address (put) [DMA align/dummy]
Read even DMC address (get) [DMC DMA read]
Read even PC address (put) [OAM DMA align]
Read $xx00 (get) [OAM DMA read]
Write $2004 (put) [OAM DMA write]
----Even A0's end here-----
Read $xx01 (get) [OAM DMA read]

With a looping 1 byte DMC sample or with the implicit stop DMC DMA bug on some G CPUs and all H CPUs, it should be possible to stay even for as much as 14 cycles:

Write $4015 (get)
Read STA ($01),Y opcode (put)
Read STA ($01),Y operand (get)
Read $01 for low pointer byte (put)
-----Even A0's start here-----
Read $02 for high pointer byte (get) [DMC DMA halt]
Read $02 (put) [DMC DMA dummy]
Read even DMC address (get) [DMC DMA read]
Read $02 (put) [DMC DMA halt]
Read $02 (get) [DMC DMA dummy]
Read $02 (put) [DMC DMA alignment]
Read even DMC address (get) [DMC DMA read]
Read $02 for high pointer byte (put)
Read $4014 for index adjustment (get)
Write $4014 (put)
Read even PC (get) [OAM DMA halt]
Read even PC (put) [OAM DMA alignment]
Read $xx00 (get) [OAM DMA read]
Write $2004 (put) [OAM DMA write]
-----Even A0's stop here-----
Read $xx01 (get) [OAM DMA read]

I wouldn't be surprised if there's a way to make this a little longer, but this is what came to mind for now. You should refer to https://www.nesdev.org/wiki/DMA for the specific timings of these DMA cases.

Statistics: Posted by Fiskbit — Fri Nov 29, 2024 3:23 pm

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